Design and characterization of a clock distribution circuit for QCA

In this paper we introduce and characterize a novel circuit design for low power clock distribution for quantumdot cellular automata (QCA) systems. The characterization of the clocking circuitry includes an evaluation of: the coupling capacitances among the wires and with the ground plane; the dissipative effects of the wires and the substrate; the phase shift between neighboring wires; and the number of wires driven by the same clock line. The electrical characteristics of the clocking circuitry are a function of the chosen design parameters. The clock tree is initially modeled as an RC circuit. A resonant RLC circuit is then proposed, and its power dissipation performance is compared to an RC circuit as a function of the quality factor Q of the resonating circuit. It is shown that this approach can greatly reduce the power dissipated in the clocking layer of a QCA circuit.